Education Standards
syllabus
MICRO CONTROLLER 8051 for Diploma Students
Overview
In this Course we learn about history, terminology, block diagram, working and applications of 8051.
A microcontroller is an electronic device belonging to the microcomputer family. These are fabricated using the VLSI technology on a single chip. There are microcontrollers available in the present market with different word length starting from 4 bit, 8 bit, 64 bit to 128 bit.
MICRO CONTROLLER Subject Introduction
OBJECTIVES:
- On completion of the following units of syllabus contents, the students must be able to
- Explain Architecture of 8051 Microcontroller.
- Explain the functions of various registers.
- Understand interrupt structure of 8051.
- Understand serial data communication concepts.
- Understand the programming techniques.
- Explain various addressing modes.
- Write simple programs using 8051.
- Understand the block diagram and control word formats for peripheral devices.
- Understand how to interface with RS232C.
- Understand how to interface with 8255.
- Understand various application of 8051 Microcontroller
TOPICS AND ALLOCATION:
Unit | Topic | Time (Hrs.) |
I | Architecture & Instruction set of 8051 | 19 |
II | Programming Examples | 13 |
III | I/O and Timer | 15 |
IV | Interrupt and Serial Communication | 16 |
V | Interfacing Techniques | 19 |
| Revision – Test | 8 |
| TOTAL | 90 |
Introduction to Micro Processor & Micro controller
History of Microprocessor
Evolution of Microprocessors
We can categorize the microprocessor according to the generations or according to the size of the microprocessor:
First Generation (4 - bit Microprocessors)
The first generation microprocessors were introduced in the year 1971-1972 by Intel Corporation. It was named Intel 4004 since it was a 4-bit processor.
It was a processor on a single chip. It could perform simple arithmetic and logical operations such as addition, subtraction, Boolean OR and Boolean AND.
I had a control unit capable of performing control functions like fetching an instruction from storage memory, decoding it, and then generating control pulses to execute it.
Second Generation (8 - bit Microprocessor)
The second generation microprocessors were introduced in 1973 again by Intel. It was a first 8 - bit microprocessor which could perform arithmetic and logic operations on 8-bit words. It was Intel 8008, and another improved version was Intel 8088.
Third Generation (16 - bit Microprocessor)
The third generation microprocessors, introduced in 1978 were represented by Intel's 8086, Zilog Z800 and 80286, which were 16 - bit processors with a performance like minicomputers.
Fourth Generation (32 - bit Microprocessors)
Several different companies introduced the 32-bit microprocessors, but the most popular one is the Intel 80386.
Fifth Generation (64 - bit Microprocessors)
From 1995 to now we are in the fifth generation. After 80856, Intel came out with a new processor namely Pentium processor followed by Pentium Pro CPU, which allows multiple CPUs in a single system to achieve multiprocessing.
ARCHITECTURE & INSTRUCTION SET OF 8051
ARCHITECTUREOF 8051
Comparison of Microprocessor and Microcontroller - Block diagram of Microcontroller –Functions of each block - Pin details of 8051 – ALU –ROM– RAM – Memory Organization of 8051 - Special function registers –Program Counter – PSW register – Stack - I/O Ports – Timer – Interrupt – Serial Port – Oscillator and Clock - Clock Cycle – State - Machine Cycle –Instruction cycle – Reset – Power on Reset – Overview of 8051 family
The pin diagram of 8051 microcontroller looks as follows −
Pins 1 to 8 − These pins are known as Port 1. This port doesn’t serve any other functions. It is internally pulled up, bi-directional I/O port.
Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial values.
Pins 10 to 17 − These pins are known as Port 3. This port serves some functions like interrupts, timer input, control signals, serial communication signals RxD and TxD, etc.
Pins 18 & 19 − These pins are used for interfacing an external crystal to get the system clock.
Pin 20 − This pin provides the power supply to the circuit.
Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port. Higher order address bus signals are also multiplexed using this port.
Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a signal from the external program memory.
Pin 30 − This is EA pin which stands for External Access input. It is used to enable/disable the external memory interfacing.
Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to demultiplex the address-data signal of port.
Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order address and data bus signals are multiplexed using this port.
Pin 40 − This pin is used to provide power supply to the circuit.
The 8051 microcontroller is an 8-bit microcontroller. Let us see the major components of 8051 microcontroller and their functions.
An 8051 microcontroller has the following 12 major components:
1. ALU (Arithmetic and Logic Unit)
2. PC (Program Counter)
3. Registers
4. Timers and counters
5. Internal RAM and ROM
6. Four general purpose parallel input/output ports
7. Interrupt control logic with five sources of interrupt
8. Serial date communication
9. PSW (Program Status Word)
10. Data Pointer (DPTR)
11. Stack Pointer (SP)
12. Data and Address bus.
1. ALU
All arithmetic and logical functions are carried out by the ALU.
Addition, subtraction with carry, and multiplication come under arithmetic operations.
Logical AND, OR and exclusive OR (XOR) come under logical operations.
2. Program Counter (PC)
A program counter is a 16-bit register and it has no internal address. The basic function of program counter is to fetch from memory the address of the next instruction to be executed. The PC holds the address of the next instruction residing in memory and when a command is encountered, it produces that instruction. This way the PC increments automatically, holding the address of the next instruction.
3. Registers
Registers are usually known as data storage devices. 8051 microcontroller has 2 registers, namely Register A and Register B. Register A serves as an accumulator while Register B functions as a general purpose register. These registers are used to store the output of mathematical and logical instructions.
The operations of addition, subtraction, multiplication and division are carried out by Register A. Register B is usually unused and comes into picture only when multiplication and division functions are carried out by Register A. Register A also involved in data transfers between the microcontroller and external memory.
8051 microcontroller also has 7 Special Function Registers (SFRs). They are:
1. Serial Port Data Buffer (SBUF)
2. Timer/Counter Control (TCON)
3. Timer/Counter Mode Control (TMOD)
4. Serial Port Control (SCON)
5. Power Control (PCON)
6. Interrupt Priority (IP)
7. Interrupt Enable Control (IE)
4. Timers and Counters
Synchronization among internal operations can be achieved with the help of clock circuits which are responsible for generating clock pulses. During each clock pulse a particular operation will be carried out, thereby, assuring synchronization among operations. For the formation of an oscillator, we are provided with two pins XTAL1 and XTAL2 which are used for connecting a resonant network in 8051 microcontroller device. In addition to this, circuit also consists of four more pins. They are,
Internal operations can be synchronized using clock circuits which produce clock pulses. With each clock pulse, a particular function will be accomplished and hence synchronization is achieved. There are two pins XTAL1 and XTAL2 which form an oscillator circuit which connect to a resonant network in the microcontroller. The circuit also has 4 additional pins -
1. EA: External enable
2. ALE: Address latch enable
3. PSEN: Program store enable and
4. RST: Reset.
Quartz crystal is used to generate periodic clock pulses.
5. Internal RAM and ROM
ROM
A code of 4K memory is incorporated as on-chip ROM in 8051. The 8051 ROM is a non-volatile memory meaning that its contents cannot be altered and hence has a similar range of data and program memory, i.e, they can address program memory as well as a 64K separate block of data memory.
RAM
The 8051 microcontroller is composed of 128 bytes of internal RAM. This is a volatile memory since its contents will be lost if power is switched off. These 128 bytes of internal RAM are divided into 32 working registers which in turn constitute 4 register banks (Bank 0-Bank 3) with each bank consisting of 8 registers (R0 - R7). There are 128 addressable bits in the internal RAM.
6. Four General Purpose Parallel Input/Output Ports
The 8051 microcontroller has four 8-bit input/output ports. These are:
PORT P0: When there is no external memory present, this port acts as a general purpose input/output port. In the presence of external memory, it functions as a multiplexed address and data bus. It performs a dual role.
PORT P1: This port is used for various interfacing activities. This 8-bit port is a normal I/O port i.e. it does not perform dual functions.
PORT P2: Similar to PORT P0, this port can be used as a general purpose port when there is no external memory but when external memory is present it works in conjunction with PORT PO as an address bus. This is an 8-bit port and performs dual functions.
PORT P3: PORT P3 behaves as a dedicated I/O port
7. Interrupt Control
An event which is used to suspend or halt the normal program execution for a temporary period of time in order to serve the request of another program or hardware device is called an interrupt. An interrupt can either be an internal or external event which suspends the microcontroller for a while and thereby obstructs the sequential flow of a program.
There are two ways of giving interrupts to a microcontroller – one is by sending software instructions and the other is by sending hardware signals. The interrupt mechanism keeps the normal program execution in a "put on hold" mode and executes a subroutine program and after the subroutine is executed, it gets back to its normal program execution. This subroutine program is also called an interrupt handler. A subroutine is executed when a certain event occurs.
In 8051, 5 sources of interrupts are provided. They are:
a) 2 external interrupt sources connected through INT0 and INT1
b) 3 external interrupt sources- serial port interrupt, Timer Flag 0 and Timer Flag 1.
The pins connected are as follows:
1. ALE (Address Latch Enable) - Latches the address signals on Port P0
2. EA (External Address) - Holds the 4K bytes of program memory
3. PSEN (Program Store Enable) - Reads external program memory
4. RST (Reset) - Reset the ports and internal registers upon start up
8. Serial Data Communication
A method of establishing communication among computers is by transmitting and receiving data bits is a serial connection network. In 8051, the SBUF (Serial Port Data Buffer) register holds the data; the SCON (Serial Control) register manages the data communication and the PCON (Power Control) register manages the data transfer rates. Further, two pins - RXD and TXD, establish the serial network.
The SBUF register has 2 parts – one for storing the data to be transmitted and another for receiving data from outer sources. The first function is done using TXD pin and the second function is done using RXD pin.
There are 4 programmable modes in serial data communication. They are:
1. Serial Data mode 0 (shift register mode)
2. Serial Data mode 1 (standard UART)
3. Serial Data mode 2 (multiprocessor mode)
4. Serial Data mode 3
9. PSW (Program Status Word)
Program Status Word or PSW is a hardware register which is a memory location which holds a program's information and also monitors the status of the program this is currently being executed. PSW also has a pointer which points towards the address of the next instruction to be executed. PSW register has 3 fields namely are instruction address field, condition code field and error status field. We can say that PSW is an internal register that keeps track of the computer at every instant.
Generally, the instruction of the result of a program is stored in a single bit register called a 'flag'. The are7 flags in the PSW of 8051. Among these 7 flags, 4 are math flags and 3 are general purpose or user flags.
The 4 Math flags are:
• Carry (c)
• Auxiliary carry (AC)
• Overflow (OV)
• Parity (P)
The 3 General purpose flags or User flags are:
• FO
• GFO
• GF 1
10. Data Pointer (DPTR)
The data pointer or DPTR is a 16-bit register. It is made up of two 8-bit registers called DPH and DPL. Separate addresses are assigned to each of DPH and DPL. These 8-bit registers are used for the storing the memory addresses that can be used to access internal and external data/code.
11. Stack Pointer (SP)
The stack pointer (SP) in 8051 is an 8-bit register. The main purpose of SP is to access the stack. As it has 8-bits it can take values in the range 00 H to FF H. Stack is a special area of data in memory. The SP acts as a pointer for an address that points to the top of the stack.
12. Data and Address Bus
A bus is group of wires using which data transfer takes place from one location to another within a system. Buses reduce the number of paths or cables needed to set up connection between components.
There are mainly two kinds of buses - Data Bus and Address Bus
Data Bus: The purpose of data bus is to transfer data. It acts as an electronic channel using which data travels. Wider the width of the bus, greater will be the transmission of data.
Address Bus: The purpose of address bus is to transfer information but not data. The information tells from where within the components, the data should be sent to or received from. The capacity or memory of the address bus depends on the number of wires that transmit a single address bit.
Overview of 8051 family
Common and Basic Features of 8051 CPU based Microcontroller
8051 Microcontroller is equipped with lots of advanced features with following features:-
- On Chip ROM 4 KB bytes Program Read Only Memory.
- Total 128 bytes of Random Access Memory on Chip.
- Four 8051 Memory Register Banks
- User defined 128 software flags
- Bidirectional 8 bit data bus to fetch data
- Unidirectional 16 bit bus to communicate
- General Purpose Registers 32 each with 8 bit
- Total 16 bit Timers for timing operations.
- Internal and External two interrupts
- Four Ports with 8 bit data transfer
- 16 Bit program data pointer and counter
- It also has few special features like UARTs, Operational Amp
- Analog to digital converter ADC, DAC.
INSTRUCTION SET OF 8051
Instruction set of 8051 – Classification of 8051 Instructions - Data transfer instructions – Arithmetic Instructions – Logical instructions –Branching instructions – Bit Manipulation Instructions
- Writing a Program for any Microcontroller consists of giving commands to the Microcontroller in a particular order in which they must be executed in order to perform a specific task. The commands to the Microcontroller are known as a Microcontroller’s Instruction Set.
- Just as our sentences are made of words, a Microcontroller’s (for that matter, any computer) program is made of Instructions. Instructions written in a program tell the Microcontroller which operation to carry out.
- An Instruction Set is unique to a family of computers. This tutorial introduces the 8051 Microcontroller Instruction Set also called as the MCS-51 Instruction Set.
- As the 8051 family of Microcontrollers are 8-bit processors, the 8051 Microcontroller Instruction Set is optimized for 8-bit control applications. As a typical 8-bit processor, the 8051 Microcontroller instructions have 8-bit Opcodes. As a result, the 8051 Microcontroller instruction set can have up to 28 = 256 Instructions
Argument | Description |
addr11 | An 11-bit address destination. This argument is used by ACALL and AJMP instructions. The target of the CALL or JMP must lie within the same 2K page as the first byte of the following instruction. |
addr16 | A 16-bit address destination. This argument is used by LCALL and LJMP instructions. |
bit | A direct addressed bit in internal data RAM or SFR memory. |
direct | An internal data RAM location (0-127) or SFR (128-255). |
immediate | A constant included in the instruction encoding. |
offset | A signed (two's complement) 8-bit offset (-128 to 127) relative to the first byte of the following instruction. |
@Ri | An internal data RAM location (0-255) addressed indirectly through R0 or R1. |
Rn | Register R0-R7. |
Alphabetical List of Instructions
|
|
DATA TRANSFER | ARITHMETIC | LOGICAL | BOOLEAN | PROGRAM BRANCHING |
MOV | ADD | ANL | CLR | LJMP |
MOVC | ADDC | ORL | SETB | AJMP |
MOVX | SUBB | XRL | MOV | SJMP |
PUSH | INC | CLR | JC | JZ |
POP | DEC | CPL | JNC | JNZ |
XCH | MUL | RL | JB | CJNE |
XCHD | DIV | RLC | JNB | DJNZ |
| DA A | RR | JBC | NOP |
|
| RRC | ANL | LCALL |
|
| SWAP | ORL | ACALL |
|
|
| CPL | RET |
|
|
|
| RETI |
|
|
|
| JMP |
ta moving / handling Instructions:
Mnemonics | Operational description | Addressing mode | No. of bytes occupied | No. of cycles used |
Mov a,#num | Copy the immediate data num in to acc | immediate | 2 | 1 |
Mov Rx,a | Copy the data from acc to Rx | register | 1 | 1 |
Mov a,Rx | Copy the data from Rx to acc | register | 1 | 1 |
Mov Rx,#num | Copy the immediate data num in to Rx | immediate | 2 | 1 |
Mov a,add | Copy the data from direct address add to acc | direct | 2 | 1 |
Mov add,a | Copy the data from acc to direct address add | direct | 2 | 1 |
Mov add,#num | Copy the immediate data num in to direct address | direct | 3 | 2 |
Mov add1,add2 | Copy the data from add2 to add1 | direct | 3 | 2 |
Mov Rx,add | Copy the data from direct address add to Rx | direct | 2 | 2 |
Mov add,Rx | Copy the data from Rx to direct address add | direct | 2 | 2 |
Mov @Rp,a | Copy the data in acc to address in Rp | Indirect | 1 | 1 |
Mov a,@Rp | Copy the data that is at address in Rp to acc | Indirect | 1 | 1 |
Mov add,@Rp | Copy the data that is at address in Rp to add | Indirect | 2 | 2 |
Mov @Rp,add | Copy the data in add to address in Rp | Indirect | 2 | 2 |
Mov @Rp,#num | Copy the immediate byte num to the address in Rp | Indirect | 2 | 1 |
Movx a,@Rp | Copy the content of external add in Rp to acc | Indirect | 1 | 2 |
Movx a,@DPTR | Copy the content of external add in DPTR to acc | Indirect | 1 | 2 |
Movx @Rp,a | Copy the content of acc to the external add in Rp | Indirect | 1 | 2 |
Movx @DPTR,a | Copy the content of acc to the external add in DPTR | Indirect | 1 | 2 |
Movc a,@a+DPTR | The address is formed by adding acc and DPTR and its content is copied to acc | indirect | 1 | 2 |
Movc a, @a+PC | The address is formed by adding acc and PC and its content is copied to acc | indirect | 1 | 2 |
Push add | Increment SP and copy the data from source add to internal RAM address contained in SP | Direct | 2 | 2 |
Pop add | copy the data from internal RAM address contained in SP to destination add and decrement SP | direct | 2 | 2 |
Xch a, Rx | Exchange the data between acc and Rx | Register | 1 | 1 |
Xch a, add | Exchange the data between acc and given add | Direct | 2 | 1 |
Xch a,@Rp | Exchange the data between acc and address in Rp | Indirect | 1 | 1 |
Xchd a, @Rp | Exchange only lower nibble of acc and address in Rp | indirect | 1 | 1 |
Logical Instructions: –
Mnemonics | Operational description | Addressing mode | No. of bytes occupied | No. of cycles used |
Anl a, #num | AND each bit of acc with same bit of immediate num, stores result in acc | Immediate | 2 | 1 |
Anl a, add | AND each bit of acc with same bit of content in add, stores result in acc | Direct | 2 | 1 |
Anl a, Rx | AND each bit of acc with same bit of content of Rx, stores result in acc | Register | 1 | 1 |
Anl a, @Rp | AND each bit of acc with same bit of content of add given by Rp, stores result in acc | Indirect | 1 | 1 |
Anl add, a | AND each bit of acc with same bit of direct add num, stores result in add | Direct | 2 | 1 |
Anl add, #num | AND each bit of direct add with same bit of immediate num, stores result in add | direct | 3 | 2 |
orl a, #num | OR each bit of acc with same bit of immediate num, stores result in acc | Immediate | 2 | 1 |
orl a, add | OR each bit of acc with same bit of content in add, stores result in acc | Direct | 2 | 1 |
orl a, Rx | OR each bit of acc with same bit of content of Rx, stores result in acc | Register | 1 | 1 |
orl a, @Rp | OR each bit of acc with same bit of content of add given by Rp, stores result in acc | Indirect | 1 | 1 |
orl add, a | OR each bit of acc with same bit of direct add num, stores result in add | Direct | 2 | 1 |
orl add, #num | OR each bit of direct add with same bit of immediate num, stores result in add | direct | 3 | 2 |
Xrl a, #num | XOR each bit of acc with same bit of immediate num, stores result in acc | Immediate | 2 | 1 |
Xrl a, add | XOR each bit of acc with same bit of content in add, stores result in acc | Direct | 2 | 1 |
Xrl a, Rx | XOR each bit of acc with same bit of content of Rx, stores result in acc | Register | 1 | 1 |
Xrl a, @Rp | XOR each bit of acc with same bit of content of add given by Rp, stores result in acc | Indirect | 1 | 1 |
Xrl add, a | XOR each bit of acc with same bit of direct add num, stores result in add | Direct | 2 | 1 |
Xrl add, #num | XOR each bit of direct add with same bit of immediate num, stores result in add | direct | 3 | 2 |
Clr a | Clear each bit of acc | Direct | 1 | 1 |
Cpl a | Complement each bit of acc | direct | 1 | 1 |
Anl c, b | AND carry with given bit b, stores result in carry | — | 2 | 2 |
Anl c, /b | AND carry with complement of given bit b, stores result in carry | — | 2 | 2 |
Orl c, b | OR carry with given bit b, stores result in carry | — | 2 | 2 |
Orl c, /b | OR carry with complement of given bit b, stores result in carry | — | 2 | 2 |
Cpl c | Complement carry flag | — | 1 | 1 |
Cpl b | Complement bit b | — | 2 | 1 |
Clr c | Clear carry flag | — | 1 | 1 |
Clr b | Clear given bit b | — | 2 | 1 |
Mov c, b | Copy bit b to carry | — | 2 | 1 |
Mov b, c | Copy carry to bit b | — | 2 | 2 |
Setb c | Set carry flag | — | 1 | 1 |
Setb b | Set bit b | — | 2 | 1 |
Rl a | Rotate acc one bit left | — | 1 | 1 |
Rr a | Rotate acc one bit right | — | 1 | 1 |
Rlc a | Rotate acc one bit left with carry | — | 1 | 1 |
Rrc a | Rotate acc one bit right with carry | — | 1 | 1 |
Swap a | Exchange upper and lower nibble of acc | — | 1 | 1 |
Arithmetic Instructions: –
Mnemonics | Operational description | Addressing mode | No. of bytes occupied | No. of cycles used |
Inc a | Add 1 to acc | Register | 1 | 1 |
Inc Rr | Add 1 to register Rr | Register | 1 | 1 |
Inc add | Add 1 to the content of add | Direct | 2 | 1 |
Inc @rp | Add 1 to the content of the address in Rp | indirect | 1 | 1 |
Inc DPTR | Add 1 to DPTR | Register | 1 | 2 |
dec a | Subtract 1 from acc | Register | 1 | 1 |
dec Rr | Subtract 1 from Rr | Register | 1 | 1 |
dec add | Subtract 1 from content of add | Direct | 2 | 1 |
dec @rp | Subtract 1 from the content of address | indirect | 1 | 1 |
Add a, #num | Add the immediate num with acc and stores result in acc | immediate | 2 | 1 |
Add a, Rx | Add the data in Rx with acc and stores result in acc | Register | 1 | 1 |
Add a, add | Add the data in add with acc and stores result in acc | Direct | 2 | 1 |
Add a, @Rp | Add the data at the address in Rp with acc and stores result in acc
| Indirect | 1 | 1 |
Addc a,#num | Add the immediate num with acc and carry, stores result in acc | immediate | 2 | 1 |
Addc a, Rx | Add the data in Rx with acc and carry, stores result in acc | Register | 1 | 1 |
Addc a, add | Add the data in add with acc and carry, stores result in acc | Direct | 2 | 1 |
Addc a, @Rp | Add the data at the address in Rp with acc and carry, stores result in acc | Indirect | 1 | 1 |
Subb a, #num | Subtract immediate num and carry from acc; stores the result in acc | immediate | 2 | 1 |
Subb a, add | Subtract the content of add and carry from acc; stores the result in acc | Register | 1 | 1 |
Subb a, Rx | Subtract the data in Rx and carry from acc; stores the result in acc | Direct | 2 | 1 |
Subb a, @Rp | Subtract the data at the address in Rp and carry from acc; stores the result in acc | Indirect | 1 | 1 |
Mul ab | Multiply acc and register B. store the lower byte of result in acc and higher byte in B | — | 1 | 4 |
div ab | divide acc by register B. store quotient in acc and remainder in B | — | 1 | 4 |
Da a | After addition of two packed BCD numbers, adjust the sum to decimal format | — | 1 | 1 |
Branching Instructions: –
Mnemonic | Operational description | No of bytes occupied | No. of cycles used |
Jc label | Jump to label if carry is set to 1 | 2 | 2 |
Jnc label | Jump to label if carry is cleared to 0 | 2 | 2 |
Jb b,label | Jump to label if given bit is set to 1 | 3 | 2 |
Jnb b,label | Jump to label if given bit is cleared to 0 | 3 | 2 |
Jbc b,label | Jump to label if given bit is set. Clear the bit | 3 | 2 |
Cjne a, add, label | Compare the content of accumulator with the content of given address and if not equal jump to label | 3 | 2 |
Cjne a, #num, label | Compare the content of accumulator with immediate number and if not equal jump to label | 3 | 2 |
Cjne Rx, #num, label | Compare the content of Rx with the immediate number and if not equal jump to label | 3 | 2 |
Cjne @Rp, #num, label | Compare the content of location in Rp with immediate number and if not equal jump to label | 3 | 2 |
Djnz Rx, label | Decrement the content of Rx and jump to the label if it is not zero | 2 | 2 |
Djnz add, label | Decrement the content of address and jump to the label if it is not zero | 3 | 2 |
Jz label | Jump to the label if content of accumulator is 0 | 2 | 2 |
Jnz label | Jump to the label if content of accumulator is not 0 | 2 | 2 |
Jmp @a+dptr | Jump to the address created by adding the contents on accumulator and dptr | 1 | 2 |
Ajmp sadd | Take a jump to absolute short range address sadd | 2 | 2 |
Ljmp ladd | Take a jump to absolute long range address sadd | 3 | 2 |
Sjmp radd | Take a jump to relative address radd | 2 | 2 |
nop | Short form of no operation means do nothing and go to next instruction | 1 | 1 |
Acall sadd | Pushes the content of Acc on stack and load it will absolute short range address sadd | 2 | 2 |
Lcall ladd | Pushes the content of Acc on stack and load it will absolute long range address sadd | 3 | 2 |
Ret | returns from subroutine by restoring the Acc from stack using pop operation | 1 | 2 |
reti | Returns from interrupt subroutine by restoring Acc from stack using pop operation | 1 | 2 |
Bit-oriented Instructions
Similar to logic instructions, bit-oriented instructions perform logic operations. The difference is that these are performed upon single bits.
Here some simple assembly language programs for 8051 microcontroller are given to understand the operation of different instructions and to understand the logic behind particular program. First the statement of the program that describes what should be done is given. Then the solution is given which describes the logic how it will be done and last the code is given with necessary comments.
Statement 1: – exchange the content of FFh and FF00h
Solution: – here one is internal memory location and other is memory external location. so first the content of ext memory location FF00h is loaded in acc. then the content of int memory location FFh is saved first and then content of acc is transferred to FFh. now saved content of FFh is loaded in acc and then it is transferred to FF00h.
Mov dptr, #0FF00h ; take the address in dptr
Movx a, @dptr ; get the content of 0050h in a
Mov r0, 0FFh ; save the content of 50h in r0
Mov 0FFh, a ; move a to 50h
Mov a, r0 ; get content of 50h in a
Movx @dptr, a ; move it to 0050h
Duplication and Subtraction
Statement 2: – store the higher nibble of r7 in to both nibbles of r6
Solution: –first we shall get the upper nibble of r7 in r6. Then we swap nibbles of r7 and make OR operation with r6 so the upper and lower nibbles are duplicated
Mov a, r7 ; get the content in acc
Anl a, #0F0h ; mask lower bit
Mov r6, a ; send it to r6
Swap a ; xchange upper and lower nibbles of acc
Orl a, r6 ; OR operation
Mov r6, a ; finally load content in r6
Statement 3: – treat r6-r7 and r4-r5 as two 16 bit registers. Perform subtraction between them. Store the result in 20h (lower byte) and 21h (higher byte).
Solution: – first we shall clear the carry. Then subtract the lower bytes afterward then subtract higher bytes.
Clr c ; clear carry
Mov a, r4 ; get first lower byte
Subb a, r6 ; subtract it with other
Mov 20h, a ; store the result
Mov a, r5 ; get the first higher byte
Subb a, r7 ; subtract from other
Mov 21h, a ; store the higher byte
Division & Data Transfer
Statement 4: – divide the content of r0 by r1. Store the result in r2 (answer) and r3 (reminder). Then restore the original content of r0.
Solution:-after getting answer to restore original content we have to multiply answer with divider and then add reminder in that.
Mov a, r0 ; get the content of r0 and r1
Mov b, r1 ; in register A and B
Div ab ; divide A by B
Mov r2, a ; store result in r2
Mov r3, b ; and reminder in r3
Mov b, r1 ; again get content of r1 in B
Mul ab ; multiply it by answer
Add a, r3 ; add reminder in new answer
Mov r0, a ; finally restore the content of r0
Statement 5: – transfer the block of data from 20h to 30h to external location 1020h to 1030h.
Solution: – here we have to transfer 10 data bytes from internal to external RAM. So first, we need one counter. Then we need two pointers one for source second for destination.
Mov r7, #0Ah ; initialize counter by 10d
Mov r0, #20h ; get initial source location
Mov dptr, #1020h ; get initial destination location
Nxt: Mov a, @r0 ; get first content in acc
Movx @dptr, a ; move it to external location
Inc r0 ; increment source location
Inc dptr ; increase destination location
Djnz r7, nxt ; decrease r7. if zero then over otherwise move next