MICROCONTROLLERS AND APPLICATIONS

Created April 29, 2024 by Purushottam Kamble

Addressing modes

The 8051 instructions use eight addressing modes. These are:

1. Register Addressing 

2. Direct Addressing

3. Indirect Addressing

4. Immediate Addressing

5. Relative Addressing

6. Absolute Addressing

7. Long Addressing

8. Indexed Addressing


1. Register Addressing

In this mode a register has the operand. Depending on the instruction used by the user the register may be the first operand, the second operand or it can be both. The data on which the instruction operates is from eight registers which are labelled R0 to R7 (Rn, in general). These registers are to be found in one of four register banks, at a time only one can be active. On power-up or reset, the default register bank is bank 0. The format of an instruction using register addressing:

For example, to Add the contents of accumulator A with that of register R3, the following instruction is used:

                                           ADD A, R3

2. Direct Addressing

Instructions using direct addressing refers directly to a location in memory.

The plus point of this instruction is that this one is fast but it is not as fast as immediate addressing mode. The minus point of this type of instruction is that the code depends on the correct data always being present at same location. only one memory location is required and no calculations.

For example,

                                         MOV 46H, A

which transfer the content of the accumulator to memory location 46H.

3. Indirect Addressing

In this mode of addressing as it's name indicates the instruction performs an operation on the data whose address is contained in register R0 or R1. in this type of instruction we provide the register, in which the address of the another register is stored where the data is stored or to be stored.

For example,

                                          MOV A, @R0

which transfer the data to the accumulator from the register whose address is stored in the register R0.

4. Immediate Addressing

This is the simplest form of addressing. In an instruction that uses immediate addressing, the operand is present in the instruction. An # symbol is used before an operand in assembly language to indicate immediate addressing mode. The operand may be a numeric constant, a symbolic variable, or an arithmetic expression using constants, symbols, and operators. 

For example,

                                          MOV A, #77H

which transfer the data 77H to the accumulator.

5. Relative Addressing

it is also called program counter relative addressing. A relative address is nothing but an 8-bit signed value, which is added to the current address in the program counter to form the address of the next instruction executed. The range for such a jump instruction is –128 to +127 locations. 

For example, 

                                           JZ rel

performs the following operations:

                                        (PC) <= (PC) + 2 

                                        IF (A) = 0

                                                      THEN (PC) <= (PC) + rel

                                         ELSE continue

The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice.


6. Absolute Addressing

Only two instructions are there that uses this addressing: ACALL (absolute call) and AJMP (absolute jump). These type of instructions perform branching within the current 2K page of program memory. The branch address is obtained by successively concatenating the five high-order bits of the program counter, bits 5 – 7 of the op-code, and the second byte of the instruction. The diagram illustrate how this is done:

Note that the branch destination address is within the same 2K page of program memory because the highest most five address bits are the same as those in the program counter before the branch is taken.


7. Long Addressing

Only two instructions use this addressing mode. These instructions are LCALL addr16 and LJMP addr16. Both the instructions of three byte instructions. In which the op-code being the first byte and the following two bytes are the address high byte and address low-byte respectively. These instructions enable the program to branch to anywhere within the full 64 K bytes of program memory address space.


8. Indexed Addressing

In this mode the 16-bit address in a base register is added to a positive offset to form an effective address for the jump indirect instruction JMP @A+DPTR, and the two move code byte instructions MOVC A,@A+DPTR and MOVC A,@A+PC. The base register in the jump instruction is the data pointer and the positive offset is held in the accumulator. For the move instructions the base register can either be the data pointer or the program counter, and again the positive offset is in the accumulator. The operations of these three instructions are as follows:

                                              JMP @A+DPTR (PC) <= (A) +(DPTR)

                                              MOVC A,@A+DPTR (A) <= ((A) + (DPTR))

Instruction set

Arithmetic Instructions

Mnemonics

Description

Bytes

Instruction Cycles

ADD A, Rn

A  A + Rn

1

1

ADD A, direct

A  A + (direct)

2

1

ADD A, @Ri

A  A + @Ri

1

1

ADD A, #data

A  A + data

2

1

ADDC A, Rn

A  A + Rn + C

1

1

ADDC A, direct

A   A + (direct) + C

2

1

ADDC A, @Ri

A  A + @Ri + C

1

1

ADDC A, #data

A  A + data + C

2

1

DA A

Decimal adjust accumulator

1

1

DIV AB

Divide A by B 
A  quotient 
B  remainder

1

4

DEC A

A  A -1

1

1

DEC Rn

Rn  Rn - 1

1

1

DEC direct

(direct)  (direct) - 1

2

1

DEC @Ri

@Ri  @Ri - 1

1

1

INC A

A  A+1

1

1

INC Rn

Rn  Rn + 1

1

1

INC direct

(direct)  (direct) + 1

2

1

INC @Ri

@Ri  @Ri +1

1

1

INC DPTR

DPTR  DPTR +1

1

2

MUL  AB

Multiply A by B 
A  low byte (A*B) 
B  high byte (A* B)

1

4

SUBB A, Rn

A  A - Rn - C

1

1

SUBB A, direct

A  A - (direct) - C

2

1

SUBB A, @Ri

A  A - @Ri - C

1

1

SUBB A, #data

A  A - data - C

2

1

Logical Instructions

Mnemonics

Description

Bytes

Instruction Cycles

ANL A, Rn

A  A AND Rn

1

1

ANL A, direct

A  A AND (direct)

2

1

ANL A, @Ri

A  A AND @Ri

1

1

ANL A, #data

A  A AND data

2

1

ANL direct, A

(direct)  (direct) AND A

2

1

ANL direct, #data

(direct)  (direct) AND data

3

2

CLR A

A 00H

1

1

CPL A

AA

1

1

ORL A, Rn

A  A OR Rn

1

1

ORL A, direct

A  A OR (direct)

1

1

ORL A, @Ri

A  A OR @Ri

2

1

ORL A, #data

A  A OR data

1

1

ORL direct, A

(direct)  (direct) OR A

2

1

ORL direct, #data

(direct)  (direct) OR data

3

2

RL A

Rotate accumulator left

1

1

RLC A

Rotate accumulator left through carry

1

1

RR A

Rotate accumulator right

1

1

RRC A

Rotate accumulator right through carry

1

1

SWAP A

Swap nibbles within Acumulator

1

1

XRL A, Rn

A  A EXOR Rn

1

1

XRL A, direct

A  A EXOR (direct)

1

1

XRL A, @Ri

A  A EXOR @Ri

2

1

XRL A, #data

A  A EXOR data

1

1

XRL direct, A

(direct)  (direct) EXOR A

2

1

XRL direct, #data

(direct)  (direct) EXOR data

3

2

Data Transfer Instructions

Mnemonics

Description

Bytes

Instruction Cycles

MOV A, Rn

A  Rn

1

1

MOV A, direct

A  (direct)

2

1

MOV A, @Ri

A  @Ri

1

1

MOV A, #data

A  data

2

1

MOV Rn, A

Rn  A

1

1

MOV Rn, direct

Rn  (direct)

2

2

MOV Rn, #data

Rn  data

2

1

MOV direct, A

(direct)  A

2

1

MOV direct, Rn

(direct)  Rn

2

2

MOV direct1, direct2

(direct1)  (direct2)

3

2

MOV direct, @Ri

(direct) @Ri

2

2

MOV direct, #data

(direct)  #data

3

2

MOV @Ri, A

@Ri  A

1

1

MOV @Ri, direct

@Ri  (direct)

2

2

MOV @Ri, #data

@Ri  data

2

1

MOV DPTR, #data16

DPTR  data16

3

2

MOVC A, @A+DPTR

A  Code byte pointed by A + DPTR

1

2

MOVC A, @A+PC

A  Code byte pointed by A + PC

1

2

MOVC A, @Ri

A  Code byte pointed by Ri 8-bit address)

1

2

MOVX A, @DPTR

A  External data pointed by DPTR

1

2

MOVX @Ri, A

@Ri  A (External data - 8bit address)

1

2

MOVX @DPTR, A

@DPTR  A(External data - 16bit address)

1

2

PUSH direct

(SP)  (direct)

2

2

POP direct

(direct)  (SP)

2

2

XCH Rn

Exchange A with Rn

1

1

XCH direct

Exchange A with direct byte

2

1

XCH @Ri

Exchange A with indirect RAM

1

1

XCHD A, @Ri

Exchange least significant nibble of A with that of indirect RAM

1

1

Boolean Variable Instructions

Mnemonics

Description

Bytes

Instruction Cycles

CLR C

C-bit  0

1

1

CLR bit

bit  0

2

1

SET C

C  1

1

1

SET bit

bit  1

2

1

CPL C

C  

1

1

CPL bit

bit   

2

1

ANL C, /bit

C  C . 

2

1

ANL C, bit

C  C. bit

2

1

ORL C, /bit

 C C + 

2

1

ORL C, bit

C  C + bit

2

1

MOV C, bit

C bit

2

1

MOV bit, C

bit  C

2

2

Program Branching Instructions

Mnemonics

Description

Bytes

Instruction Cycles

ACALL addr11

PC + 2  (SP) ; addr 11 PC

2

2

AJMP addr11

Addr11  PC

2

2

CJNE A, direct, rel

Compare with A, jump (PC + rel) if not equal

3

2

CJNE A, #data, rel

Compare with A, jump (PC + rel) if not equal

3

2

CJNE Rn, #data, rel

Compare with Rn, jump (PC + rel) if not equal

3

2

CJNE @Ri, #data, rel

Compare with @Ri A, jump (PC + rel) if not equal

3

2

DJNZ Rn, rel

Decrement Rn, jump if not zero

2

2

DJNZ direct, rel

Decrement (direct), jump if not zero

3

2

JC rel

Jump (PC + rel) if C bit = 1

2

2

JNC rel

Jump (PC + rel) if C bit = 0

2

2

JB bit, rel

Jump (PC + rel) if bit = 1

3

2

JNB bit, rel

Jump (PC + rel) if bit = 0

3

2

JBC bit, rel

Jump (PC + rel) if bit = 1

3

2

JMP @A+DPTR

A+DPTR  PC

1

2

JZ rel

If A=0, jump to PC + rel

2

2

JNZ rel

If A ≠ 0 , jump to PC + rel

2

2

LCALL addr16

PC + 3  (SP), addr16  PC

3

2

LJMP addr 16

Addr16  PC

3

2

NOP

No operation

1

1

RET

(SP)  PC

1

2

RETI

(SP)  PC, Enable Interrupt

1

2

SJMP rel

PC + 2 + rel  PC

2

2

JMP  @A+DPTR

A+DPTR  PC

1

2

JZ  rel

If A = 0. jump PC+ rel

2

2

JNZ  rel

If A ≠ 0, jump PC + rel

2

2

NOP

No operation

1

1


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